Title :
A compact threshold-voltage model of MOSFETs with stack high-k gate dielectric
Author :
Ji, F. ; Xu, J.P. ; Chen, J.J. ; Xu, H.X. ; Li, C.X. ; Lai, P.T.
Author_Institution :
Dept. of Electron. Sci. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China
Abstract :
In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interlayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interlayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current.
Keywords :
MOSFET; high-k dielectric thin films; 2D simulations; compact threshold-voltage model; equivalent oxide thickness; gate leakage current; low-k interlayer EOT; stack high-k gate-dielectric MOSFET; threshold-voltage behaviors; threshold-voltage roll-off; Dielectric substrates; Doping; High K dielectric materials; High-K gate dielectrics; Leakage current; MOS devices; MOSFETs; Permittivity; Poisson equations; Threshold voltage; MOSFET; Threshold voltage; stack gate dielectric;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394286
