Design architecture of generic DFT/DCT 1D and 2D engine controlled by SW instructions

Author

Hassan, Hanan M. ; Shalash, Ahmed F. ; Hamed, Hisham M.

Author_Institution

Fac. of Eng., Cairo Univ., Cairo, Egypt

fYear

2010

fDate

6-9 Dec. 2010

Firstpage

84

Lastpage

87

Abstract

In this paper, a hardware implementation for generic DFT/IDFT DCT/IDCT 1D (N-point) and 2D (N × M point) processor is proposed, as N/M in the form of 2^x × 3^y to support different communication and signal processing applications. An in-place bank of 2 N-word dual-port memories with a continuous address generator is adopted to accommodate high-speed applications. This engine is controlled by software instructions running on a simple embedded processor to provide more flexibility in switching between different modes and desired number of points, instead of a complex hardware controller. This software flexibility also allows the user to adapt the operations on data to match his needs.

Keywords

discrete Fourier transforms; discrete cosine transforms; embedded systems; microprocessor chips; random-access storage; 2N-word dual-port memory; RAM memory; communication application; embedded processor; generic DFT-IDFT DCT-IDCT 1D processor; generic DFT-IDFT DCT-IDCT 2D processor; hardware controller; in-place bank; signal processing application; software flexibility; Instruction sets; WiMAX; DCT; DFT; configurable HW;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-7454-7

Type

conf

DOI

10.1109/APCCAS.2010.5774751

Filename

5774751