Mixed-level modeling for network on chip infrastructure in SoC design

We present a concise, fast, accurate, efficient mixed-level full-system based realistic application-oriented simulation platform in this paper which aims to evaluate the cycle-accurate behavior of interconnection component thus help developers to explore more optimized NoC architecture. A trace-driven transaction-level simulation environment is built to get realistic traffic patterns for interconnection. We design wrappers to translate the transaction-level traffic patterns into cycle-accurate flits. We implement routers at cycle-accurate level which use fixed five-step pipeline architectures pursuing more details in design, while implement peripherals (IP cores) at transaction-level following TLM 2.0 standard. Due to we only need to focus on the performance of interested part, that is the interconnection, under the premise of keeping the accuracy of interconnection simulation, the utilization of transaction-level models makes the peripheral modeling in full-system simulation environment more efficient, lightweight, configurable and scalable.