A UWB down convert circuit and measurement

This article presents a UWB receiver, which is made by the chips designed by our group in SMIC0.18 um process, This receiver was verified by the measurement, With the help of FPGA it can synthesis 2.8G~3.98 GHz LO frequency by changing the PLL and reference frequency, with reference frequency 21 MHz, division ratio 1/160, it can be locked at 3.36 GHz with the phase noise of -83 dBc/Hz, the internal Digital VGA could be digitally controlled by FPGA with 30 dB tuning range. Though Chip scope verification, This receiver can demodulate 500 MHz Bandwidth signal without error bit rate by connected the receiver and transmitter with RF line return loss of 40 dB, the power consumption of this receiver is 60 mW.