SOI implementation of low-voltage and high-temperature MOSFET-C continuous-time filters

Thin-film fully-depleted (FD) SOI MOSFETs are very promising for the implementation of highly-linear MOS resistors. It has been demonstrated both theoretically and experimentally that, due to their low body effect, the drain current of FD SOI MOS structures presents much lower signal distortion than bulk Si counterparts, when the transistors are biased in the strong-inversion linear regime and a sine signal is applied at the source or drain terminal, the gate voltage being used as a DC control voltage for fine tuning of resistor value. Balanced structures combining one or two MOS pairs-to attenuate odd or odd-and-even order harmonics respectively-are used to implement continuous-time (CT) filters of the MOSFET-C type which are of great interest for the integration of low-voltage analog filters. This work discusses the first SOI MOSFET-C filter implementations and investigates their potential for low-voltage and high-temperature applications. Basic first-order sections are first studied to gain physical insight on the problem but can next be cascaded to generate higher-order filters as is finally demonstrated