Low IR drop and low power parallel CAM design using gated power transistor technique

In this paper we analyzed the IR drop problem in large scale content addressable memory (CAM) and proposed a simple yet efficient gated power transistor technique. Each row of CAM cells is powered by two metal rails, one for the memory element and another one for the comparison transistors and the match lines. The latter rail is powered by a row-based transistor, which presents a physical “gate” to limit the peak current during comparison. Smart control scheme is proposed to automatically turn the power transistor off using a feedback delay loop. Simulation reports 96% reduction in IR drop and 64% save in total energy consumption, for a conceptual 8K-word CAM macros based on Chartered 0.13μm CMOS technology.