SAR ADC that is configurable to optimize yield

This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any errors due to incomplete settling of the internal DAC can be corrected in later steps of the successive approximation. In general, using more of the overlapping successive- approximation (SA) steps (and faster steps) permits faster SAR ADC sampling rates but increases power consumption. Thus this power-speed tradeoff can be utilized to compensate for CMOS process variations of each ADC chip; if the chip is slow, we can use more-rapid SA steps and more overlapping steps to satisfy the sampling speed specification (at the cost of increasing power consumption); if the chip is fast, we can use fewer (and slower) steps to satisfy the sampling speed specification and also achieve lower power consumption. We use automatic test equipment (ATE) for production testing and to store the appropriate algorithm data that enables the sampling rate specification to be met in flash memory on the chip. The DAC output settling margin is determined by checking comparator output at each step and confirming that ADC final output is correct. Our measurements demonstrate the effectiveness of this approach.