High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

This paper presents a high speed Single-Stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding Read-Out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600μw power consumption from a 3.3v power supply by using TSMC model of 0.35μm CMOS technology. Total active area of proposed comparator and Read-Out circuit is about 300μm2.