Memory size reduction for LDPC layered decoders

LDPC coding has attracted much attention due to its high performance, and it has been widely used in telecommunication systems. This paper focuses on the decoder hardware architecture, especially on memory size reduction, which is an important part of the entire area cost. The design has been post-layout simulated using a UMC 0.18 micron technology at a clock speed of 74 MHz. Using the proposed 3-level memory structure together with the described control logic, the required number of bits of memory can be reduced by up to 34.9% compared to prior approaches.