Notice of RetractionReliability optimized CMOS gates

Notice of Retraction

After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.

We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.

The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.

Redundancy at the device/transistor-level has been proposed as the most effective way to improve reliability (as early as 1956). With the exceptional reliability of the CMOS transistors the semiconductor industry was able to fabricate, research on device-level redundancy has dragged for several decades. However, with the increasing sensitivities to noise (both intrinsic and extrinsic) and variations (due to the massive scaling) of CMOS transistors, interest on device-level redundancy has been reviving during the last decade. In this paper we investigate transistor sizing as a method that can significantly reduce the probability of failure due to threshold voltage variations, while having almost no impact on the area. For a given reliability target, we try to identify several transistor sizing combinations for optimizing the trade-off between reliability and the traditional power-area-delay optimization parameters. The simulation results will show that adjusting the sizing of the nMOS and pMOS transistors can have dramatical effects on reliability (e.g., improving the reliability of classical NOR-2 gates by more than five orders of magnitude while also reducing the occupied area by about 10%).