A 5.5-GHz multi-modulus frequency divider in 0.35μm SiGe BiCMOS technology for delta-sigma fractional-N frequency synthesizers

A 5.5-GHz pulse-swallow multi-modulus frequency divider for delta-sigma fractional-N frequency synthesizers is demonstrated in this paper. The frequency divider is composed of a synchronous current mode logic (CML) divide-by-4/5 prescaler, an asynchronous CML divide-by-4 divider and a digital programmable A-M counter. The proposed divider is optimized for high frequency and low power operation; the asynchronous divide-by-4 divider is triggered by the falling edge instead of the rising edge of the synchronous divide-by-4/5 prescaler to relax the timing requirement of the feedback modulus-select signal; the feedback modulus-select signal is provided by a NOR gate instead of AND gate, and the AM counter feedback is feed at the last NOR gate in the feedback chain to minimize its delay and increase the maximum operation frequency. A prototype has been implemented in 0.35μm SiGe BiCMOS technology, occupying 0.1mm² active silicon areas. The operating frequency is 5.5GHz; the divide ratio is 256~511 with step of 1; and current consumption is 6.8mA in 3V power supply.