Area-efficient parallel-prefix Ling adders

Efficient addition of binary numbers plays a very important role in the design of dedicated as well as general purpose processors for the implementation of arithmetic and logic units, branch decision, and floating-point operations, address generations, etc. Several methods have been reported in the literature for the fast and hardware-efficient realization of binary additions. Among these methods, parallel-prefix addition schemes have received much of attentions, since they provide many design choices for delay/area-efficient implementations and optimization of tradeoffs. In this paper, we have proposed area-efficient approach for the design of parallel-prefix Ling adders. We have achieved the area efficiency by computing the real carries, based on the Ling carries produced by the lower bit positions. Using the proposed method, the number of logic levels can be reduced by one, which leads to reduction of delay as well as significant saving of area complexity of the adder. We have implemented the proposed adders using 0.18μm CMOS technology; and from the synthesis results, we find that our proposed adders could achieve up to 35% saving of area over the previously reported parallel-prefix Ling adders under the same delay constraints.