High-speed and low power unified dual-field multiplier in GF (P) and GF (2m)

This paper presents a new hardware architecture for a unified multiplier, which operates in two types of finite field: GF (P) and GF (2^m). We present a simple but highly useful modification of the conventional hardware implementation of accumulation in finite field over GF (P) and GF (2^m). This new design uses parallel one´s counters to accumulate the binary partial product bit in GF (P) and further uses a T flip-flop for binary extension field. The proposed multiplier in GF (2^m) achieves 11.76% and 30.23% gain in speed for (8, 16, 32) and (64, 128) bit operands respectively and an average 3.92% reduction in power consumption. The unified dual field multiplier achieves 19.3% and 14.3% gain in speed and reduction in power consumption respectively for 8 bits operand. The proposed multiplier is scalable for operands of any size. The multiplier uses the LSB-first bit serial architecture for multiplication in GF (P) and GF (2^m), other than Montgomery multiplication algorithm, which mostly employs existing dual field multipliers.