DocumentCode
3229043
Title
Implementing Pfairness on a symmetric multiprocessor
Author
Holman, Philip ; Anderson, James H.
Author_Institution
North Carolina Univ., Chapel Hill, NC, USA
fYear
2004
fDate
25-28 May 2004
Firstpage
544
Lastpage
553
Abstract
We consider the implementation of a Pfair scheduler on a symmetric multiprocessor (SMP). Simulations presented herein suggest that bus contention resulting from simultaneous scheduling decisions can substantially degrade performance. To correct this problem, we propose a staggered model for Pfair scheduling under which scheduling points are uniformly distributed over time.
Keywords
multiprocessing systems; processor scheduling; real-time systems; Pfair scheduler; symmetric multiprocessor; Cost function; Degradation; Performance analysis; Processor scheduling; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time and Embedded Technology and Applications Symposium, 2004. Proceedings. RTAS 2004. 10th IEEE
ISSN
1545-3421
Print_ISBN
0-7695-2148-7
Type
conf
DOI
10.1109/RTTAS.2004.1317302
Filename
1317302
Link To Document