An all-digital de-skew clock generator for arbitrary wide range delay

An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-μm CMOS technology. The clock generator achieves a measured RMS jitter of 8.3 ps at an 800-MHz clock with 10 cycles settling time. The chip area is 0.825×0.605 mm² and the power consumption is 53mW from a 1.8V supply.