Modeling and minimizing variations of gate-all-around multiple-channel nanowire TFTs

In this paper we describe the electrical performance of poly-Si gate-all-around (GAA) thin-film transistors (TFTs) featuring multiple-channel nanowires (NWs). To minimize the variation in the electrical characteristics of these TFTs, we compared the effects of several approach, including the use of a multiple-gate structure, the number of multiple channels, and NH₃ plasma treatment. Relative to a tri-gate structure, the GAA devices exhibited superior performance. In addition, the presence of multiple channels efficiently reduced the variation in the electrical characteristics. Devices featuring 16-cnannel present the minimized standard deviation in both threshold voltage and subthreshold swing (30 mV and 11.4 mV/dec, respectively). The device-to-device variation due to random grain-size distribution in poly-Si GAA NW TFT was modeled by Poisson area scatter model. The electrical measurements of poly-Si GAA NW TFTs and the model are in agreement. Finally, NH₃ plasma treatment of the GAA TFTs featuring multiple channels further decreased the electrical variations and improved the device performance.