Design and analysis of cost-efficient IFFT/FFT processor chip for wireless OFDM systems

In this paper, a cost-efficient IFFT/FFT processor with its fixed-point analysis is presented for wireless orthogonal frequency division multiplexing (OFDM) system. The IFFT/FFT processor is multiplierless architecture, and the nonzero bits of twiddle factors (TW) are minimized to reduce the structure (or the number of the hardwired adder) by the proposed classification of TWs and hardware sharing. On the other hand, the minimum wordlength (WL) of the TWs and input signals can be determined by the fix-point analysis. The proposed IFFT/FFT processor can achieve packet error rate(PER); 0.1 for the test vehicle IEEE 802.11a single-input-single-output(SISO)-OFDM system and slight symbol error rate(SER) loss for the IEEE 802.11n multi-input-multi-output(MIMO)-OFDM system. The core area of the one processor chip is 0.57um×0.565um with 0.18um CMOS process. Besides, the power consumption is 7.74 mw with 1.8 V supply voltage and 40 Mhz system clock.