Implementation of highly accurate NMOS Vt based clamping technique in low current comparator

This paper presents a circuit implementation of a simple but accurate NMOS Vt based clamping technique to decrease the logic transition delay in an ultra low ground current comparator. In a very low current comparator the output logic delay is predominantly set by the speed of slew limited decision making nodes and hence limiting their wide swing by clamping them around the decision point is one of the ways to reduce that delay. In this paper an innovative NMOS threshold based clamping technique is proposed to clamp the gate of the NMOS of output logic stage in both going high and going low which ensures high speed logic transition along with very accurate clamping threshold without using too much bias current. Simulation results with analysis and the layout of the comparator with the proposed clamping network in 0.5μm CMOS process has also been presented in the paper.