A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems

Existing SoC debug techniques mainly target bus-based systems. They are not readily applicable to the emerging system that use network-on-chip (NoC) as on-chip communication scheme. In this paper, we present the detailed design of a novel debug probe (DP) inserted between the core under debug (CUD) and the NoC. With embedded configurable triggers, delay control and timestamping mechanism, the proposed DP is very effective for inter-core transaction analysis as well as controlling embedded cores´ debug processes. Experimental results show the functionalities of the proposed DP and its area overhead.