Development of low power DAC with pseudo Fibonacci sequence

Author

Kubokawa, Ryota ; Ohshima, Takashi ; Tomar, Abhishek ; Ramesh, Pokharel ; Kanaya, Haruichi ; Yoshida, Keiji

Author_Institution

Grad. Sch. of Inf. Sci. & Eng., Kyushu Univ., Fukuoka, Japan

fYear

2010

fDate

6-9 Dec. 2010

Firstpage

370

Lastpage

373

Abstract

A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage. Also we fabricated the prototype 6-bit DAC with pseudo Fibonacci sequence and tested. The measured power consumption is very low and almost the same value as a simulated value.

Keywords

CMOS analogue integrated circuits; Fibonacci sequences; digital-analogue conversion; low-power electronics; power consumption; CMOS technology; digital-analog converter; low power DAC; power consumption; pseudo Fibonacci sequence; size 0.18 mum; unary sequence; voltage 3.3 V; word length 12 bit; word length 6 bit; CMOS integrated circuits; Current measurement; Layout; Power demand; Power measurement; Prototypes; Semiconductor device measurement; Digital-analog converter (DAC); low-power consumption; pseudo Fibonacci sequence;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-7454-7

Type

conf

DOI

10.1109/APCCAS.2010.5774936

Filename

5774936