An improved design method for multi-bits reused booth multiplier

In order to solve the question for the 32-bit multiplier to do a variety of bit-length multiplication fast in the form of reusing resource on the FPGA, radix-4 booth modified algorithm is studied, and a bit-length controller is designed to control some bits, partial product generator and fast adder´s structure are improved, so as to reuse most of the hardware resource in 8-bit or 16-bit multiplication. The multiplier works with not only 32-bit but also two 16-bit or four 8-bit data at one clock, ensures the speed and saves the chip area at the same time.