A highly linear open-loop high-speed CMOS sample-and-hold

This paper presents an open loop high speed CMOS sample and hold with improved linearity. Previously, an open-loop S/H and a method of charge injection cancellation were introduced [1]. However, it requires many clock phases. In this paper a new charge injection cancellation scheme has been introduced with improved linearity than the previous one while its implementation is simpler. The proposed S/H achieves 76dB linearity at 500MS/s sampling rate and at nyquist input frequency by using TSMC model of 0.35μm CMOS technology.