Title :
A highly linear open-loop high-speed CMOS sample-and-hold
Author :
Mousazadeh, Morteza ; Hadidi, Khayrollah ; Khoei, Abdollah
Author_Institution :
Microelectron. Res. Lab., Urmia Univ., Urmia, Iran
Abstract :
This paper presents an open loop high speed CMOS sample and hold with improved linearity. Previously, an open-loop S/H and a method of charge injection cancellation were introduced [1]. However, it requires many clock phases. In this paper a new charge injection cancellation scheme has been introduced with improved linearity than the previous one while its implementation is simpler. The proposed S/H achieves 76dB linearity at 500MS/s sampling rate and at nyquist input frequency by using TSMC model of 0.35μm CMOS technology.
Keywords :
CMOS analogue integrated circuits; charge injection; high-speed integrated circuits; sample and hold circuits; CMOS technology; TSMC model; charge injection cancellation; highly linear open-loop high-speed CMOS sample-and-hold; nyquist input frequency; size 0.35 mum; Capacitors; Clocks; Linearity; Logic gates; Switches; Switching circuits; Transistors;
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5774968
