Systolic-array 3D wave-digital beam filters

3D IIR beam/cone filter-banks are derived from beam transfer functions of 2D/3D LC-ladder low-pass networks. Such filters are obtained using 3D frequency-planar filters as building blocks, and lead to highly-selective RF beamforming capabilities over wide bandwidths. High computational complexity necessitates high-performance computational hardware for useful throughput. A massively-parallel systolic-array hardware architecture is proposed for the FPGA-based hardware acceleration of arbitrary-order spatial frequency-planar beam broadband digital filters. The proposed architecture is based on multidimensional wave-digital-filters, and leads to a synchronous systolic-array of locally interconnected parallel processing core modules (PPCMs), which enable 3D beam filtering at a throughput of one frame per clock cycle. An example using a Xilinx Virtex-4 Sx35 FPGA, for a 6×6 array of PPCMs, is described.