High-speed low-power bootstrapped level converter for dual supply systems

This paper proposes a high-speed and low-power bootstrapped level converter for dual-supply systems. The proposed level converter adopts a voltage bootstrapping at the gate of pull-down transistors to achieve improved driving speed and reduced contention problem. Simulation results in a 0.13-um CMOS process indicated that the proposed level converter reduces the propagation delay up to 64% and the power-delay product up to 49% as compared to conventional level converters.