• DocumentCode
    3231380
  • Title

    Dependability, power, and performance trade-off on a multicore processor

  • Author

    Sato, Toshinori ; Funaki, Toshimasa

  • Author_Institution
    Kyushu Univ., Fukuoka
  • fYear
    2008
  • fDate
    21-24 March 2008
  • Firstpage
    714
  • Lastpage
    719
  • Abstract
    As deep submicron technologies are advanced, we face new challenges, such as power consumption and soft errors. A naive technique, which utilizes emerging multicore processors and relies upon thread-level redundancy to detect soft errors, is power hungry. It consumes at least two times larger power than the conventional single-threaded processor does. This paper investigates a trade-off between dependability and power on a multicore processor, which is named multiple clustered core processor (MCCP). It is proposed to adapt processor resources according to the requested performance. A new metric to evaluate a trade-off between dependability, power, and performance is proposed. It is the product of soft error rate and the popular energy-delay product. We name it energy, delay, and upset rate product (ED UP). Detailed simulations show that the MCCP exploiting the adaptable technique improves the EDUP by up to 21% when it is compared with the one exploiting the naive technique.
  • Keywords
    low-power electronics; microprocessor chips; redundancy; deep submicron technologies; energy-delay product; multicore processor; multiple clustered core processor; soft error rate; thread-level redundancy; Breakdown voltage; Delay; Energy consumption; Error analysis; Fault detection; Microarchitecture; Multicore processing; Redundancy; Single event upset; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
  • Conference_Location
    Seoul
  • Print_ISBN
    978-1-4244-1921-0
  • Electronic_ISBN
    978-1-4244-1922-7
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2008.4484044
  • Filename
    4484044