DocumentCode
3231885
Title
An efficient ODT calibration scheme for improved signal integrity in memory interface
Author
Kalyan, Gudipati ; Srinivas, M.B.
Author_Institution
Centre for VLSI & Embedded Syst., IIIT Hyderabad, Hyderabad, India
fYear
2010
fDate
6-9 Dec. 2010
Firstpage
1211
Lastpage
1214
Abstract
An Input Output (IO) Buffer for memory Interface is proposed with the concept of a merged driver which helps in improving the linearity of the driver with a reduced area. A novel calibration scheme is proposed which can adjust larger driver resistance and termination impedance changes for temperature and voltage drifts in a fewer cycles of system clock which will improve the valid data window.
Keywords
DRAM chips; calibration; driver circuits; ODT calibration scheme; driver resistance; input output buffer; memory interface; signal integrity; system clock; termination impedance changes; valid data window; Calibration; Capacitance; Driver circuits; Impedance; Receivers; Resistance; Resistors; Calibration of ODT; DDR3; SSTL;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location
Kuala Lumpur
Print_ISBN
978-1-4244-7454-7
Type
conf
DOI
10.1109/APCCAS.2010.5775020
Filename
5775020
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