Title :
High performance 600 V smart power technology based on thin layer silicon-on-insulator
Author :
Letavic, T. ; Arnold, E. ; Simpson, M. ; Aquino, R. ; Bhimnathwala, H. ; Egloff, R. ; Emmerik, A. ; Wong, S. ; Mukherjee, S.
Author_Institution :
Philips Electron. North American Corp., Briarcliff Manor, NY, USA
Abstract :
A high-performance 600 V smart power technology has been developed in which novel lateral double-diffused MOS transistors (LDMOS) are merged with a BiCMOS process flow for the construction of power integrated circuits on bonded silicon-on-insulator (BSOI) substrates. All active and passive device structures have been optimized for fabrication on BSOI layers which are less than 1.5 μm-thick, with buried oxide layers in the range of 2.0 to 3.0 μm-thick. Complete dielectric isolation processing is straightforward due to the use of a thin SOI active device layer. A dual field plate design of the high-voltage devices results in at least a factor-of-two reduction in specific on-resistance over conventional LDMOS structures for a given breakdown voltage
Keywords :
BiCMOS integrated circuits; buried layers; integrated circuit measurement; isolation technology; power MOSFET; power integrated circuits; silicon-on-insulator; 1.5 mum; 2 to 3 mum; 600 V; BSOI substrates; BiCMOS process flow; BiCMOS/DMOS integrated process; LDMOS; bonded silicon-on-insulator; breakdown voltage; buried oxide layers; dielectric isolation processing; dual field plate design; lateral double-diffused MOS transistors; power integrated circuits; smart power technology; specific on-resistance; thin SOI active device layer; thin layer silicon-on-insulator; Bonding; Circuits; Dielectric devices; Dielectric substrates; Fabrication; Implants; MOSFETs; North America; Silicon on insulator technology; Voltage;
Conference_Titel :
Power Semiconductor Devices and IC's, 1997. ISPSD '97., 1997 IEEE International Symposium on
Conference_Location :
Weimar
Print_ISBN :
0-7803-3993-2
DOI :
10.1109/ISPSD.1997.601428
