Shallow trench isolation etch process for 0.2 μm trench capacitor DRAM technology

Author

Karzhavin, Yuri

Author_Institution

White Oak Semicond., Sandston, VA, USA

fYear

1999

fDate

1999

Firstpage

239

Lastpage

245

Abstract

This paper presents results of the STI etch process developed for 64 MB Trench Capacitor DRAM technology, scalable for future generations of the product as well. An aspect ratio of 2.5 was achieved. High uniformity of the trench depths and after etch Critical Dimensions (ACI CD) are demonstrated. A low etch bias <0.01 μm was achieved. This manufacturable STI process for sub-0.2 μm technologies was developed for applications in an MRlE etcher with an electrostatic chuck (ESC) and Silicon shadow ring. The Si-ring provided 60-100% improvement in the STI depth and ACI CD stability across the wafer. Mean time between chamber cleans and cost of the process kit consumable parts improved 30 - 50%

Keywords

CMOS memory circuits; DRAM chips; integrated circuit manufacture; isolation technology; sputter etching; 0.2 mum; 64 Mbit; MRlE etcher; STI depth; STI etch process; Si; Si-SiO₂-Si₃N₄; after etch critical dimensions; aspect ratio; chamber cleaning; electrostatic chuck; low etch bias; manufacturable STI process; process kit consumable parts; shallow trench isolation etch; silicon shadow ring; trench capacitor DRAM technology; trench depth uniformity; Argon; Capacitors; Chemistry; Dielectrics; Etching; Isolation technology; Random access memory; Semiconductor device manufacture; Silicon; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5217-3

Type

conf

DOI

10.1109/ASMC.1999.798233

Filename

798233