Achieving near-MLD performance with soft information-set decoders implemented in FPGAs

This paper describes a design strategy that makes viable hardware implementations of Information-Set (IS)-based decoders with near-MLD performance. This is achieved through three main developments: i) a criterion that reduces the number of candidate codewords, without significant performance loss; ii) a modified, hardware-friendlier version of the Dorsch algorithm; and iii) detailed circuit analysis and optimization in all critical parts (matrix manipulators, data sorter, data memory, and data path) that comprise the final circuit. The proposed architecture was implemented in FPGA devices, for several code sizes, showing speeds from 80 MHz (for large codes) to 160 MHz (for small codes), and efficient resources usage, with the number of LUTs ranging from 400 (for small codes) to 5,600 (large codes). In pipelined operation, the number of clock cycles to decode a received word is equal to m (number of candidate codewords).