Negative ESD robustness of a novel anti-ESD TGFPTD SOI LDMOS

A novel anti-ESD TGFPTD (Trench Gate and Field Plate and Trench Drain) SOI LDMOS was proposed firstly for improve ESD robustness of TGFPTD SOI LDMOS in this paper. The proposed device was obtained by introducing an additional n⁺ implantation and rapid thermal annealing into the widen p-well region of conventional TGFPTD SOI LDMOS. 2D simulation of the proposed device upon a negative current pulse stimulus of HBM indicates that a hybrid conduction mechanism of parasitic diodes, BJTs, SCR, resistors, capacitors and Schottky diode exists during ESD period. Moreover, the gate voltage is clamped below 11% of the breakdown voltage of gate oxide and the induced gate charges are released in a very short time at about 1.0μs. Therefore, the proposed anti-ESD TGFPTD SOI LDMOS is featured of very high negative ESD robustness.