Development and implementation of an engineered solution for the RTP distortion problem affecting subsequent litho alignment

During advanced <0.2 μm DRAM manufacturing it is critical to utilize the low thermal budget oxidation processes. Rapid Thermal Oxidation (RTO) becomes the only feasible alternative to the conventional furnace oxidation process. However, the usage of RTO may become one of the major yield limiters, due to wafer pattern distortion during high temperature processing. As we discovered, wafer warpage is a major contributor to the subsequent overlay contact alignment problems of photolithography. To correct this problem, a new technique has been developed and implemented to compensate for the “photon box edge effect” to minimize the temperature gradient. “Near perfect” temperature control across the entire wafer becomes imperative. This paper describes and summarizes the advantages of the new method, which employs a more efficient power management technique and has been implemented for the RTO process