Effects of in-situ arsenic-doped amorphous silicon emitter process on SiGe heterojunction bipolar transistors

This paper discusses the use of a single wafer process tool to deposit As-doped amorphous silicon emitter films on double polysilicon, self-aligned SiGe heterojunction NPN bipolar transistors. In-situ processing has the advantage of reducing the number and complexity of process steps while being compatible with sub-350 nm emitter technologies. Below 350 nm implanted polysilicon emitters are expected to encounter adverse perimeter effects and the plug effect. We report increased transistor gain with amorphous silicon emitters compared with similarly doped polysilicon emitters caused by a reduction in the base current. We will demonstrate how the base current can be controlled by polysilicon deposition temperature. Also, with in-situ doping, we show how improved uniformity of the As concentration at the base-emitter junction translates into improved across-wafer uniformity for the pinch base sheet resistance