Small-Signal Analysis and Modeling of Asymmetric Source/Drain Parasitic Resistances for DRAM Access Transistors in Low-Power Applications

The small-signal conductance technique was extended to extract asymmetric source/drain parasitic resistances. It was also applied in order to analyze the t_WR delay of DRAM cell transistors in production and to develop a non-planar cell transistor such as recessed access device (RAD) for low-power DRAM cells. Factors limiting the drive current for planar and non-planar access transistors in the low-power DRAM cells were discussed