Interface Barrier Abruptness and Work Function requirements for scaling Schottky Source-Drain MOS Transistors

Author

Agrawal, Naveen ; Chen, Jingde ; Hui, Zhao ; Yeo, Yee-Chia ; Lee, Sungjoo ; Chan, Daniel S H ; Li, Ming-Fu ; Samudra, Ganesh S.

Author_Institution

Fac. of Eng., Nat. Univ. of Singapore

fYear

2006

fDate

6-8 Sept. 2006

Firstpage

139

Lastpage

142

Abstract

Schottky source-drain (S/D) MOS transistor coupled with metal gate is a promising alternative to the conventional poly-Si gate and doped S/D MOSFET technology. This paper explores through simulations the effect of metal S/D WF and the gradual change of barrier profile at the metal-semiconductor interface and in the few nanometers space around it on the n/p channel device performance. We present the S/D workfunction (WF) requirements for ultra short channel device design for the first time. Through modeling and fabrication, we also present the underlying physical explanation behind the existence of dual slope in I_d-V_g characteristics of metal S/D and gate MOSFETs

Keywords

MOSFET; Schottky barriers; Schottky gate field effect transistors; semiconductor device models; work function; I_d-V_g characteristics; MOSFET; Schottky source-drain MOS transistors; barrier profile; interface barrier abruptness; metal-semiconductor interface; n/p channel device performance; ultra short channel device design; work function; Doping; Fabrication; MOSFET circuits; Nanoscale devices; Schottky barriers; Semiconductor process modeling; Space technology; Substrates; Thermal resistance; Thermionic emission; Dual Slope; Metal Gate; Metal Source/Drain; Schottky Source-Drain; TBGD;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2006 International Conference on

Conference_Location

Monterey, CA

Print_ISBN

1-4244-0404-5

Type

conf

DOI

10.1109/SISPAD.2006.282857

Filename

4061600