DocumentCode
3233473
Title
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation
Author
Marrakchi, Zied ; Mrabet, Hayder ; Mehrez, Habib
Author_Institution
LIP6-ASIM Lab., Univ. Paris
fYear
2005
fDate
28-30 Sept. 2005
Lastpage
25
Abstract
We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power dissipation is reduced by an average of 8.5%
Keywords
field programmable gate arrays; logic design; network routing; device utilization; field programmable gate array; hierarchical FPGA clustering; multilevel partitioning approach; power consumption reduction; power dissipation reduction; routability-driven clustering; top-down clustering; Clustering algorithms; Delay; Field programmable gate arrays; Integrated circuit interconnections; Logic; Partitioning algorithms; Pins; Routing; Switches; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on
Conference_Location
Puebla City
Print_ISBN
0-7695-2456-7
Type
conf
DOI
10.1109/RECONFIG.2005.23
Filename
1592507
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