Modification of parasitic edge leakage in LOCOS-isolated SOI MOSFETS using back-gate stress

SOI MOSFETs fabricated using LOCOS isolation can suffer from source-to-drain leakage along the edge of the silicon island which degrades the subthreshold slope of the device and increases the off-state leakage current. The edge leakage is caused by a parasitic edge transistor in parallel with the main transistor. This leakage is typically more common in NMOS devices because the boron at the tip of the silicon island readily segregates into the surrounding oxide. A technique has been demonstrated which can increase the V_T of the parasitic edge transistor in LOCOS-isolated NMOS devices, thereby dramatically reducing the parasitic edge leakage without greatly affecting the main transistor. In a research/development environment, this technique offers the possibility of extracting circuit data from a lot whose leakage otherwise prevents meaningful circuit measurement, and thus provides a tool for overcoming parasitic edge leakage without the need to run additional silicon