Power/Performance Based Scalability Comparisons between Conventional and Novel Transistors Down to 32nm Technology Node

We quantify and compare the scalability of bulk, partially depleted SOI, and double gate transistors with and without high-k gate dielectric down to 32 nm technology node in terms of globally optimized power/performance curves. The novelty of work is in that it provides a quantitative tool to determine the suitable insertion point for novel transistor schemes. It also addresses optimum supply/threshold voltage, gate dielectric thickness, and doping concentration scaling, unique to different devices and circuit functional blocks