High-speed ADC dynamic performance validation: The impact of skew-corner lot testing

Author

Kim, Seokjin ; Peckerar, Martin

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD

fYear

2008

fDate

8-11 Sept. 2008

Firstpage

29

Lastpage

32

Abstract

Corner-lot process statistics have been demonstrated to provide important data on component yield and functionality. In this paper, we review the basics of this statistical approach and we show how they are applied to the dynamic performance of a high-speed (800 MS/s) dual channel 6-bit ADC. The skew-corner ADC performance test results allow us to determine (a) the quality the semiconductor fabricate process, (b) the sufficiency of the high speed ADC test and measurement equipment, and (c) which process parameters dominate yield.

Keywords

analogue-digital conversion; high-speed integrated circuits; semiconductor device testing; analog-digital conversion; corner-lot process statistics; dual channel; dynamic performance validation; high-speed ADC; measurement equipment; semiconductor fabricate process; skew-corner lot testing; word length 6 bit; Analog-digital conversion; Analytical models; Circuit testing; Fabrication; Integrated circuit measurements; Performance analysis; Process control; Sampling methods; Semiconductor device testing; Silicon; Analog-to-digital converter (ADC); corner lot; process variation; sampling; skew-corner;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON, 2008 IEEE

Conference_Location

Salt Lake Cirty, UT

ISSN

1088-7725

Print_ISBN

978-1-4244-2225-8

Electronic_ISBN

1088-7725

Type

conf

DOI

10.1109/AUTEST.2008.4662578

Filename

4662578