IC design-for-test and testability features

Author

Press, Ron

Author_Institution

Mentor Graphics Corp., Wilsonville, OR

fYear

2008

fDate

8-11 Sept. 2008

Firstpage

88

Lastpage

91

Abstract

IC test is at a mature state where automated tools are used for DFT feature insertion and pattern generation. This paper summarizes the most common digital IC design-for-test (DFT) techniques in use today. Most of the focus is on testing and validating the correct operation of ICs after fabrication. However, many of the IC DFT features can also be re-used in higher level test and in the field. In addition, some of the concepts in the well known strategies used for IC testing may be also effective for higher level of assembly test. Some of the topics presented on include scan, automatic test pattern generation (ATPG), boundary scan, built-in self-test (BIST), memory BIST and repair, secure IC test, diagnostics, and test challenges.

Keywords

automatic test pattern generation; boundary scan testing; built-in self test; design for testability; integrated circuit design; integrated circuit testing; ATPG; BIST; DFT feature insertion; IC design-for-test; automatic test pattern generation; boundary scan; built-in self-test; secure IC test; Assembly; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Costs; Design for testability; Integrated circuit testing; Logic testing; Manufacturing; ATPG; BIST; IC test; LPCT; built-in self-test; scan; structured test;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON, 2008 IEEE

Conference_Location

Salt Lake Cirty, UT

ISSN

1088-7725

Print_ISBN

978-1-4244-2225-8

Electronic_ISBN

1088-7725

Type

conf

DOI

10.1109/AUTEST.2008.4662590

Filename

4662590