A study on accelerated built-in self test of multi-Gb/s high speed interfaces

Author

Kang, Seong-Won ; Chun, Jung-Hoon ; Jun, Young-Hyun ; Kwon, Kee-Won

Author_Institution

Samsung Electron. Co., Ltd., Yongin, South Korea

fYear

2011

fDate

8-9 Dec. 2011

Firstpage

1

Lastpage

4

Abstract

An efficient built-in self test (BIST) method is proposed for accelerated bit error rate (BER) test. The BIST can intentionally generate timing and voltage offsets at the data transmitter in order to measure the timing and voltage margins by drawing stereographic BER diagram on a voltage-time plane. Linear numerical models for `BER vs. time´ and `BER vs. voltage´ are established and verified by the measurement results from various sources. The acceleration test sequence based on the linear model completes the BER test down to 10^-15 level in 150msec.

Keywords

built-in self test; error statistics; integrated circuit testing; logic testing; numerical analysis; BIST; accelerated bit error rate test; accelerated built-in self test method; acceleration test sequence; data transmitter; inter integrated circuit; linear numerical models; multiGb/s high speed interfaces; on-chip test architecture; stereographic BER diagram; test logic; timing generation; timing margin measurement; voltage margin measurement; voltage offset generation; voltage-time plane; Acceleration; Bit error rate; Built-in self-test; Fitting; Numerical models; Timing; Voltage measurement; Acceleration test; BER modeling; BIST; Self-diagnosis; Serial interface;

fLanguage

English

Publisher

ieee

Conference_Titel

Networked Embedded Systems for Enterprise Applications (NESEA), 2011 IEEE 2nd International Conference on

Conference_Location

Fremantle, WA

Print_ISBN

978-1-4673-0495-5

Type

conf

DOI

10.1109/NESEA.2011.6144937

Filename

6144937