Title :
Channel-drain lateral profile engineering for advanced CMOS on ultra-thin SOI technology
Author :
Adan, A.O. ; Kaneko, S. ; Naka, T. ; Urabe, D. ; Higashi, K. ; Kagisawa, A.
Author_Institution :
VLSI Dev. Lab., Sharp Corp., Nara, Japan
fDate :
30 Sep-3 Oct 1996
Abstract :
Fully depleted (FD) MOSFETs on SOI substrate have the potential performance required for low-voltage, high-speed applications; however controllability and low drain-source breakdown (BVdss) have been pointed out. In this work, a new transistor channel-drain lateral profile engineering approach is presented and its potential to reduce the short-channel degradation and the parasitic bipolar effect on Vth roll-off and BVdss is experimentally demonstrated in a 0.35-μm CMOS on SIMOX process
Keywords :
MOSFET; SIMOX; doping profiles; ion implantation; semiconductor device reliability; 0.35 micron; SIMOX process; Si; advanced CMOS; channel-drain lateral profile; drain-source breakdown; fully depleted MOSFETs; high-speed applications; parasitic bipolar effect; short-channel degradation; ultra-thin SOI technology; Boron; CMOS technology; Degradation; Doping profiles; Electrodes; Implants; Inverters; MOS devices; MOSFET circuits; Very large scale integration;
Conference_Titel :
SOI Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Sanibel Island, FL
Print_ISBN :
0-7803-3315-2
DOI :
10.1109/SOI.1996.552513
