Variational Compact Modeling and Simulation for Linear Dynamic Systems

In this paper, we propose a new statistical model order reduction technique called SSMOR method, that is suitable for considering both intra-die and inter-die process variations. The SSMOR generates order reduced variational models from the original variational circuits. The reduced model can be used for fast statistical performance analysis of interconnect circuits with variational power sources. The SSMOR uses statistical spectrum method to compute the variational moments and Monte Carlo sampling method via modified Krylov subspace reduction method to generate the variational reduced models. Experimental results show that explicit moment matching is not suitable for variational analysis and Krylov subspace projection method is more reliable. The proposed method can deliver about 100times speedup over the pure Monte Carlo based projection-based reduction method with less than 1 % of errors for both means and variances in statistical transient analysis