DocumentCode
3235709
Title
Architecture for the real-time implementation of three-dimensional subband video coding
Author
Hartung, John
Author_Institution
AT&T Bell Labs., Murray Hill, NJ, USA
Volume
3
fYear
1992
fDate
23-26 Mar 1992
Firstpage
225
Abstract
A multiprocessor architecture for the real-time implementation of video coding algorithms is described. This MIMD architecture provides an efficient I/O structure for processing video at various resolutions, and has a distributed frame store and I/O structure suited for the implementation of three-dimensional subband coding. A high-quality 384 kb/s coder has been implemented using the video array processor (VAP) as a research platform for developing the coding algorithm
Keywords
digital signal processing chips; image coding; image processing equipment; image sequences; parallel architectures; video signals; 384 kbit/s; AT&T DSP32C processor; MIMD architecture; multiprocessor architecture; real-time implementation; three-dimensional subband coding; video array processor; video coding; Bit rate; Computer architecture; Discrete cosine transforms; Filtering; Filters; Image reconstruction; Image sequences; Memory architecture; Motion compensation; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on
Conference_Location
San Francisco, CA
ISSN
1520-6149
Print_ISBN
0-7803-0532-9
Type
conf
DOI
10.1109/ICASSP.1992.226210
Filename
226210
Link To Document