Optimization of 1.8V I/O circuits for performance, reliability at the 100 nm technology node

Author

Menezes, V. ; Keshav, C.B. ; Gupta, S. ; Roopashree, M. ; Krishnan, Sridhar ; Amerasekera ; Palau, G.

fYear

2003

fDate

4-8 Jan. 2003

Firstpage

122

Lastpage

127

Abstract

We describe the methodology and challenges in designing robust receiver and driver buffers in a state-of-the-art sub-100 nm CMOS technology. Issues addressed are the gate voltage limitations due to very thin gate oxides, channel hot carriers, process variability and design margins. The bi-directional buffer is 90 μm×114 μm in size and has a maximum speed of 150 MHz with a 50 ohm termination.

Keywords

CMOS logic circuits; buffer circuits; circuit optimisation; circuit simulation; driver circuits; hot carriers; integrated circuit design; integrated circuit modelling; integrated circuit reliability; logic circuits; logic design; logic simulation; 1.8 V; 100 nm; 114 micron; 150 MHz; 50 ohm; 90 micron; CMOS; I/O circuit optimization; I/O circuit performance; bi-directional buffer; buffer termination impedance; channel hot carriers; circuit reliability; driver buffers; gate voltage limitations; maximum buffer speed; process variability; receiver buffers; very thin gate oxides; voltage level shifters; Application specific integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Degradation; Hot carriers; Impedance; Instruments; Logic devices; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2003. Proceedings. 16th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-1868-0

Type

conf

DOI

10.1109/ICVD.2003.1183125

Filename

1183125