DocumentCode
3235847
Title
Effects of multi-cycle sensitization on delay tests
Author
Krishnamachary, Arun ; Abraham, Jacob A.
Author_Institution
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
fYear
2003
fDate
4-8 Jan. 2003
Firstpage
137
Lastpage
142
Abstract
Existing delay test generation techniques focus on test generation for combinational blocks, and assume the inputs and outputs of the block to be unconstrained. Test application for delay tests is done by means of enhanced scan, scan shifting or functional justification; all these techniques impose minimal constraints on the inputs and the outputs of the combinational block targeted. This leads to over-testing the components for delay defects. This paper analyzes the gains associated with determining the multi-cycle (sequential) sensitization of delay tests. The advantages of determining multi-cycle sensitization is then illustrated on benchmark designs with and without a delay-specific fault model.
Keywords
automatic test pattern generation; combinational circuits; delays; logic testing; combinational circuit; defect detection; delay test generation; enhanced scan; fault model; functional justification; multi-cycle sensitization; scan shifting; Application software; Circuit faults; Circuit testing; Copper; Delay effects; Fault detection; Integrated circuit interconnections; Jacobian matrices; Microprocessors; Propagation delay;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2003. Proceedings. 16th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-1868-0
Type
conf
DOI
10.1109/ICVD.2003.1183127
Filename
1183127
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