Substrate bias effect on cycling induced performance degradation of flash EEPROMs

Author

Mahapatra, S. ; Shukuri, S. ; Bude, J.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India

fYear

2003

fDate

4-8 Jan. 2003

Firstpage

223

Lastpage

226

Abstract

Cycling induced performance degradation of flash EEPROMs has been reported for V_B=0 and V_B<0 programming operation. Compared to V_B=0, V_B<0 programming shows lower interface degradation for identical cumulative charge fluence (for program) during repetitive program/erase cycling. Reduction in programming gate current has been found to be lower for V_B<0 operation under identical interface damage as the V_B=0 case. As a consequence, programming under VB<0 condition has been found to cause lower degradation of programming time and programmed V_T due to cycling.

Keywords

PLD programming; flash memories; integrated circuit reliability; integrated memory circuits; substrates; cycling induced performance degradation; flash EEPROMs; interface degradation reduction; programming gate current reduction; repetitive program/erase cycling; substrate bias effect; Channel hot electron injection; Charge measurement; Current measurement; Degradation; EPROM; FETs; Feedback; Hot carrier injection; Impact ionization; Integrated circuit technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2003. Proceedings. 16th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-1868-0

Type

conf

DOI

10.1109/ICVD.2003.1183140

Filename

1183140