Design automation of digital circuits for partially depleted SOI-technology

Author

Sikora, A. ; Fielder, H.-L.

Author_Institution

Fraunhofer Inst. fur Mikroelektron. Schaltungen & Syst., Duisburg, Germany

fYear

1996

fDate

30 Sep-3 Oct 1996

Firstpage

108

Lastpage

109

Abstract

This paper shows that it is possible to adapt commercially available layout generators to the specific needs of partially depleted (PD)-SOI-technologies with minimal area penalty. Therefore, the requirements of SOI-specific layout techniques are investigated. A design flow for automatic layout generation is proposed. An implementation is presented with a cell library created with this generator. Measurements of test circuitry at temperatures up to 390 °C and supply voltages up to 10 V are shown

Keywords

CMOS digital integrated circuits; SIMOX; circuit layout CAD; integrated circuit layout; integrated circuit measurement; 10 V; 390 C; SIMOX substrate; SOI-CMOS; SOI-specific layout techniques; area penalty; automatic layout generation; cell library; design automation; design flow; digital circuits; layout generators; partially depleted SOI-technology; supply voltage; test circuitry; Bipolar transistor circuits; Character generation; Circuit testing; Design automation; Digital circuits; Digital systems; Electronic mail; Software libraries; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1996. Proceedings., 1996 IEEE International

Conference_Location

Sanibel Island, FL

ISSN

1078-621X

Print_ISBN

0-7803-3315-2

Type

conf

DOI

10.1109/SOI.1996.552517

Filename

552517