Title :
Mappable peripheral memory for high speed applications
Author :
Shubat, A. ; Cedar, Y. ; All, Sahal ; Sani, B. ; Nguyen, D. ; Singh, Ashutosh ; Eltan, B.
Author_Institution :
Waferscale Integration Inc., Fremont, CA, USA
Abstract :
A 30-ns mappable peripheral memory subsystem called MAP, is described. The MAP significantly enhances system performance by integrating, on the same chip, a 128-kb EPROM for program storage, a SRAM for data storage, and a programmable mapping decoder (PMD) for address decoding and mapping. The PMD is integrated into the memory-decode logic without adding up the access time. The decoder facilitates address mapping within a 2-Mb address space. The MAP is ideally suited as an expansion peripheral memory for high-speed digital signal processors, microprocessors, and microcontrollers. The 290-mil-sq. chip is implemented in a 1.2-μm CMOS EPROM process
Keywords :
CMOS integrated circuits; EPROM; integrated memory circuits; random-access storage; 1.2 micron; 128 kbit; 2 Mbit; 30 ns; CMOS EPROM process; MAP; PMD; SRAM; address decoding; address mapping; address space; chip; data storage; digital signal processors; expansion peripheral memory; mappable peripheral memory subsystem; memory-decode logic; microcontrollers; microprocessors; program storage; programmable mapping decoder; system performance; CMOS process; Clocks; Costs; Decoding; Delay; Digital signal processing; EPROM; Microcontrollers; Random access memory; System performance;
Conference_Titel :
CompEuro '89., 'VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks', Proceedings.
Conference_Location :
Hamburg
Print_ISBN :
0-8186-1940-6
DOI :
10.1109/CMPEUR.1989.93344
