Ultra low-leakage power strategies for sub-1 V VLSI: novel circuit styles and design methodologies for partially depleted silicon-on-insulator (PD-SOI) CMOS technology

As supply voltage is scaled to below 1 V, leakage power becomes significant in CMOS ICs. This paper proposes novel circuit techniques in PD-SOI technology to reduce standby power in the sub-1 V regime by over three orders of magnitude while maintaining circuit speed and with minimal overhead. Simulation results obtained using process parameters from an IBM 0.13 μm PD-SOI technology show considerable improvement over previously proposed methods as supply voltage is scaled to 0.5 V. A new design algorithm for efficient implementation of these PD-SOI standby power reduction schemes is also described.