An adaptive supply-voltage scheme for low power self-timed CMOS digital design

Author

Kuang, W. ; Yuan, J.S.

Author_Institution

Central Florida Univ., Orlando, FL, USA

fYear

2003

fDate

4-8 Jan. 2003

Firstpage

315

Lastpage

319

Abstract

This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement. This adaptive supply-voltage scheme employs the handshake signals directly to detect the speed of data path without using FIFO buffer. This leads to a very simple logic control whose power loss is negligible. Cadence SPICE simulation shows the effectiveness of this scheme for low power applications based on 0.18 μm CMOS process.

Keywords

CMOS digital integrated circuits; SPICE; circuit simulation; integrated circuit design; logic simulation; low-power electronics; power supply circuits; 0.18 micron; CMOS digital design; Cadence SPICE simulation; adaptive supply-voltage scheme; handshake signals; input data rate; logic control; low power applications; low power self-timed CMOS; power loss; speed requirement; Capacitance; Circuit simulation; Clocks; Communication system control; Delay; Dynamic voltage scaling; Logic circuits; Power dissipation; Signal detection; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2003. Proceedings. 16th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-1868-0

Type

conf

DOI

10.1109/ICVD.2003.1183156

Filename

1183156